A Simple Power Consumption Model of CMOS Buffers Briving RC Interconnect Lines
نویسندگان
چکیده
We present a simple and accurate model to compute the power dissipated in sub-micron CMOS buffers driving RC interconnect lines. The expression obtained accounts for the main effects in current sub-micron CMOS technologies as carrier velocity saturation effects, input-output coupling capacitor, output load, input slew time, device sizes and interconnect resistance. Results are compared to HSPICE simulations (level 50) and other models for a 0.18μm and a 0.35μm technologies showing significant improvements.
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تاریخ انتشار 2001